AN4078_C provides details on how to migrate an EZ-USB® FX2 based design to EZ-USB FX2LP based design. It highlights the differences between the EZ-USB FX2LP™ and EZ-USB FX2™. It also provides a brief description of the whole product support collateral available for development work with FX2LP.

Introduction

The EZ-USB FX2LP (CY7C68013A) is a next-generation USB high-speed controller. EZ-USB FX2LP enhances the functionality of the EZ-USB FX2 (CY7C68013) while minimally effecting existing designs. This application note serves two purposes:

1. Assist in migrating existing EZ-USB FX2 (also referred to as FX2 in this application note) applications to EZ-USB FX2LP (also referred to as FX2LP in this application note).
2. Assist the designers familiar with FX2 in creating FX2LP based applications.

A summary of the main items to consider while replacing the FX2 in an existing application with an FX2LP part is provided. The changes are categorized into required essential changes for all FX2LP applications migrating from FX2 and other applications based changes that might be required in your application due to additional enhanced feature in FX2LP.

Answer: When a high-speed capable device is made to work only at full speed (12 Mbps), the "This device can perform faster" pop up will appear when you connect the device to the host. This pop up appears when the ports to which the device is connected are capable of operating at high speed (480 Mbps), but the device connected is operating at full speed. You can prevent the pop up from appearing by switching the revision back to USB Specification 1.1. To do this, make the value of the bcdUSB = 0x0110 in the Device Descriptor. This change will not affect your application in any way if you intend to run the device only at full speed. By reverting back to USB Specification 1.1 in the Device Descriptor you can operate only at full speed (no high speed).

This application note discusses how to connect Cypress SRAM CY7C1399B to FX2LP over the General Programmable Interface (GPIF). It describes how to create read and write waveforms using the GPIF Designer. This application note is also useful as a reference to connect FX2LP to other SRAMs.

Introduction

The GPIF is an 8-bit or 16-bit programmable parallel interface that helps to reduce system costs by providing a glueless interface between the EZ-USB FX2LP™ and an external peripheral. It is a highly configurable and flexible piece of hardware that allows you to get the most out of your USB 2.0 design. GPIF fits into applications that need an external mastering device to exchange information. The GPIF allows the EZ-USB FX2LP to perform local bus mastering to external peripherals implementing a wide variety of protocols.

EZ-USB^® NX2LP™ USB 2.0 NAND Flash Controller

Features

• High-Speed (480-Mbps) or Full-Speed (12-Mbps) USB support
• Both common NAND page sizes supported
  • 512 bytes — Up to 1 Gbit capacity
  • 2K bytes — Up to 8 Gbit capacity
• Eight chip enable pins
  • Up to eight NAND flash single device chips
  • Up to four NAND flash dual-device chips
• Industry-standard ECC NAND flash correction
  • 1-bit error correction per 256 bytes
  • 2-bit error detection per 256 bytes
• For more, see pdf.

Introduction

The EZ-USB NX2LP (NX2LP) implements a USB 2.0 NAND Flash controller. This controller adheres to the Mass Storage Class Bulk-Only Transport Specification. The USB port of the NX2LP is connected to a host computer directly or through the downstream port of a USB hub. The Host software issues commands and data to the NX2LP and receives the status and data from the NX2LP using the standard USB protocol.

AN64408 presents the features and the resources available to speed EZ-USB NX2LP-Flex™ based design from concept to production.

Introduction

EZ-USB® NX2LP-Flex (CY7C68033/CY7C68034) is a firmware-based, programmable low power USB 2.0 NAND Flash controller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that enables feature-rich NAND Flash-based applications.

Featured in Network World Fusion News

http://www.nwfusion.com/news/tech/2002/0429tech.html

The USB specification was recently updated to improve the performance and usability of PC peripherals, opening the door to a world of high performance and high bandwidth, such as mass storage, digital video and broadband access. The speed of USB 2.0 has been increased to 480M bit/sec, a 40-fold improvement over Version 1.1.

Building a USB device requires careful attention to design details beyond the USB specification. This application note discusses design topics common to any USB device, focusing on Cypress’s EZ-USB® FX2LP™ devices. The information presented also applies to the older FX1 device and to USB devices in general. The note concludes with a schematic review checklist to help you make any USB hardware design a success, and a description of Cypress software that helps with device checkout.

Introduction

USB 2.0 brought a significant increase in bandwidth over the 1.1 specification. Offering 40x more bandwidth, it increased the importance of a good PCB design and a careful selection of components surrounding USB chips such as Cypress’s FX2LP. This application note presents a host of USB design topics that apply to any USB device at any speed, but especially to the higher speeds of USB 2.0. Although the discussions are specific to Cypress devices, they also should be helpful in any USB peripheral design.

Answer: The attached .zip file has the CyUSB3.inf and CyUSB3.sys file for FX2LP ( CY7C68013A / CY7C68014A / CY7C68015A / CY7C68016A ) and FX1 ( CY7C64713). The supported OS are   Windows XP   ( 32 and 64 bit ),   Windows Vista   ( 32 and 64 bit ) and   Windows 7   ( 32 and 64 bit ), Windows 8 (32 and 64 bit), Windows 8.1 (32 and 64 bit).

Use CyUSB3.inf in the path  (after extracting the .zip file)  shown in the below table  for the respective OS.

To match the device with the drivers, refer to the steps mentioned under the section " Matching Devices to the Driver " in the attached pdf file. Adding the VID/PID is already done in the attached inf file and the customers can skip   "Step A : Add the device's VendorID and ProductID to the CYUSB3.INF file".

Answer: Yes. The EZ-USB I²C controller serves two purposes. First, it manages the serial EEPROM interface, which operates automatically at power on, to determine the enumeration method. Second, once the CPU is up and running, firmware can access the I²C controller for general-purpose use. This makes a wide range of standard I²C peripherals available to an EZ-USB-based system. Other I²C devices can be attached to the SCL and SDA lines as long as there is no address conflict with the serial EEPROM.

The A2, A1, and A0 pins of the boot EEPROM are connected to reflect 000 (for C0 load) or 001 (for C2 load). Any other combination of A2, A1, and A0 can be used for other I²C devices connected on the bus that need to be accessed by the firmware during device operation.

Answer: As noted, the TX2UL CY7C68003 chip does not have a dedicated VBUS monitoring pin. However, for a self-powered device design, you can use a GPIO of the processor chip to monitor the upstream VBUS. Code can be written to monitor the state of this pin and thus the VBUS. Once a "low" is detected on the pin being used to monitor the VBUS, the pull-up resistor on the D+ pin can be disabled. You can enable or disable the pull up by using the "termselect" bits in the function control register.

This document describes the errata for the EZ-USB FX2/CY7C68013. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document to the device’s data sheet for a complete functional description. Contact your local Cypress Sales Representative if you have questions. 

Answer: No, the Windows XP extended host controller interface (EHCI) driver does not support high-bandwidth interrupt transfers. However, it does support high-bandwidth isochronous transfer, so an isochronous endpoint configured for three packets per microframe (3*1024 bytes) can be used for such an application.

Answer: This error occurs when the host can detect the device but is unable to enumerate it. The Microsoft® USB team has two blog posts on the possible causes and solutions to this error, Why is my USB device not detected or comes up as "Unknown Device"? and What to Try When Your USB Device is an "Unknown Device".

This issue may also occur for the following reasons (specific to FX1/FX2/FX2LP):

• The error can result from an issue with the hardware design. There are a number of items to consider when designing a board with USB devices. Please read the application note AN15456 - Guide to a Successful EZ-USB® FX2LP™ Hardware Design for guidelines on how to make a successful USB hardware design.
• If the hardware is designed correctly, the enumeration path in your firmware could have a bug. To check if this is the case, you can load a known working firmware (such as any of the CY3684 DVK examples) to your board and check if enumeration is successful. You can also let the device enumerate with the default descriptors (without any firmware) and check if enumeration is successful. If enumeration is not successful, consider the following:
  • The bug would be in either the USB descriptors file (dscr.a51) or the control request handling code (in fw.c).
  • In dscr.a51, the descriptors must be word aligned. Refer to A51 assembler directive for WORD-ALIGNING the descriptor for the assembler directive you can use to word-align the descriptors.
  • If you have edited fw.c (which is not recommended), make sure that the standard request handlers are kept intact from the original.
  • There may be an infinite loop in TD_Init() or TD_Poll() which prevents the control request handler (SetupCommand()) from being run.
• This error can be observed if the EEPROM has junk data with a valid first byte (0xC0 or 0xC2) or if the firmware is corrupt (in the C2 load).

Answer: The drive level is the maximum power you will drive into the crystal when you run the part during worst case conditions. That means 500 μW might be driven into the crystal at times. If the crystal is rated for less than 500 μW, the maximum rating on the crystal could be exceeded. This could result in faster aging of the crystal, putting it out of tolerance, or even in burn out of the crystal. Therefore, it is recommended that you use a crystal with a drive level equal to or greater than the one specified in the datasheet.

EZ-USB® FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller

Features

• USB 2.0 USB IF high speed certified (TID # 40460272)
• Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor
• Fit, form, and function compatible with the FX2
  • Pin-compatible0
  • Object-code-compatible
  • Functionally compatible (FX2LP is a superset)
• Ultra-low power: ICC No more than 85 mA in any mode
  • Ideal for bus- and battery-powered applications
• Software: 8051 code runs from:
  • Internal RAM, which is downloaded through USB
  • Internal RAM, which is loaded from EEPROM
  • External memory device (128-pin package)
• For more, see pdf

Functional Overview

USB Signaling Speed

FX2LP operates at two of the three rates defined in the USB Specification Revision 2.0, dated April 27, 2000:

• Full speed, with a signaling bit rate of 12 Mbps
• High speed, with a signaling bit rate of 480 Mbps

FX2LP does not support the Low Speed signaling mode of 1.5 Mbps.

Introduction

This application note demonstrates how to use the Cypress library for Microsoft .NET languages to implement host PC applications to communicate with Cypress's FX2LP and FX3 devices. Using this library, a Visual C#, Visual Basic, or Visual C++ program can communicate with an FX2LP or FX3-based device at a high level of abstraction.

Cypress offers firmware development tools for its USB controllers such as EZ-USB® FX2LP™ and FX3™. These firmware tools allow you to develop USB devices at a high level because most of the low-level USB “plumbing” is already in place. In many cases, high-speed FX2LP and super-speed FX3 USB devices can be developed by modifying example Cypress firmware.

Cypress also provides software development tools for the host PC in the form of a Visual Studio .NET library. This library simplifies USB coding at the Windows level. This application note introduces the .NET class library and shows how to create a Windows example to send and retrieve data using a “bulkloop” firmware example running on an FX2LP or FX3 Development Kit (DVK).

Please refer to the SuperSpeed Code Examples for more examples.

EZ-USB^® NX2LP-Flex™ Flexible USB NAND Flash Controller

CY7C68033/CY7C68034 Silicon Features

• Certified compliant for bus- or self-powered USB 2.0 operation (TID# 40490118)
• Single-chip, integrated USB 2.0 transceiver and smart SIE
• Ultra low power – 43 mA typical current draw in any mode
• Enhanced 8051 core
  • Firmware runs from internal RAM that is downloaded from NAND Flash at startup
  • No external EEPROM required
• 15 KBytes of on-chip code/data RAM
  • Default NAND firmware – 8 kB
  • Default free space – 7 kB
• For more, see pdf

Overview

Cypress Semiconductor Corporation’s EZ-USB^® NX2LP-Flex (CY7C68033/CY7C68034) is a firmware-based, programmable version of the EZ-USB NX2LP (CY7C68023/CY7C68024), which is a fixed-function, low power USB 2.0 NAND Flash controller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that enables feature-rich NAND Flash-based applications.

The Hi-Speed USB controller FX2LP CY7C68013A can be used for image sensor applications (in vendor mode) as shown in Figure 1.

Figure 1. FX2LP Interface with Image Sensor

FX2LP Pin Descriptions:

• CLKOUT: FX2LP can provide a 12-MHz, 24-MHz or 48-MHz.clock to the image sensor. Using FX2LP as the clock source you can avoid using an extra clock source for image sensor.
• IFCLK: Data transfers on FD are synchronous with IFCLK.
• SLWR:When FX2LP is used in slave FIFO mode, SLWR has to be asserted to write data to endpoint buffers.
• PA0: This GPIO can be used to monitor the start/end of the frame. You can either use PA0 as a normal GPIO or as an interrupt pin for monitoring VSYNC.
• FD[7:0]: Port B of FX2LP has to be used as 8-bit parallel interface. If the image sensor has data lines >8 (<16), it is better to connect the upper eight data lines and leave the lower data lines of the image sensor as floating. If you want to use all the data lines >8(<16), then use both port B and Port D as 16-bit parallel bit interface. In this case, FX2LP will pass two bytes of information for each pixel adding some extra redundant bits (if number of data lines > 8 (<16)) .The host application must filter out the bits that are not related to the pixel.
• I2C: FX2LP can act as an I2C master. You can configure image sensor registers using the I2C interface.

Image Sensor Pin Descriptions

• XCLK: Input pin for clock. If the image sensor doesn’t support the 12-MHz, 24-MHz, or 48-MHz clock, an external clock source must be used.
• PIXCLK: The image sensor data is synchronous to PIXCLK and must be connected to IFCLK of FX2LP.The frequency of PXICLK should be in between 5-48 MHz
• VYSNC: The frame valid signal that indicates the starting and ending of the frame.
• HSYNC: The line valid signal that indicates that there is valid data on data lines.
• D[7:0]: Output data lines that carry the image data.
• FIFOADR0 and FIFOADR1 pins of FX2LP must be connected to logic HIGH or logic LOW per the endpoint buffer that is used.

The following flowcharts provide an overview of the application:

Host Application Flowchart

FX2LP Project Flowchart

Note: 1 and 2 indicated in this flowchart are just reference points.

Note: FX2LP does not support UVC class that requires header and footer for each frame. The 8051 CPU is not fast enough to insert header and footer in between frames. Therefore, if you want to implement UVC class with FX2LP, an external FPGA must be used. The FPGA must insert the header and footer in between frames and pass the data to the FX2LP.

Create a tech support case http://www.cypress.com/support to obtain an example project.

EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge

Features

• Fixed Function Mass Storage Device - Requires no Firmware
• Two Power Modes: Self Powered and USB Bus Powered to enable Bus Powered CF (CompactFlash) Readers and Truly Portable USB Hard Drives
• Certified Compliant for USB 2.0 (TID# 40490119), the USB Mass Storage Class, and the USB Mass Storage Class Bulk-Only Transport (BOT) Specification
• Operates at High-Speed (480 Mbps) or Full-Speed (12 Mbps) USB
• Complies with ATA/ATAPI-6 Specification
• Supports 48-bit Addressing for Large Hard Drives
• Supports ATA Security Features
• Supports any ATA Command with the ATACB Function
• Supports Mode for BIOS Boot Support
• For more, see pdf
   

Introduction

The EZ-USB AT2LP™ (CY7C68300C/CY7C68301C and CY7C68320C/CY7C68321C) implements a fixed-function bridge between one USB port and one or two ATA- or ATAPI-based mass storage device ports. This bridge adheres to the Mass Storage Class Bulk-Only Transport Specification (BOT) and is intended for bus and self powered devices.

AN65209 introduces you to the EZ-USB® FX2LP™ USB 2.0 device controller. This application note helps you build a project for FX2LP and explore its various development tools, and then guides you to the appropriate documentation to accelerate in-depth learning about FX2LP.

Introduction

The Cypress EZ-USB FX2LP (hereafter abbreviated as FX2LP) is a flexible USB 2.0 PERIPHERAL controller designed to handle maximum USB 2.0 bandwidth. To take full advantage of the USB 2.0 480 Mbps signaling rate, FX2LP contains specialized hardware to buffer the USB data and connect seamlessly to a variety of highbandwidth external devices such as MCUs, ASICs, and FPGAs. After a brief introduction to USB 2.0, this application note describes FX2LP features that contribute to its high throughput.